There are a number of integrated circuit architectures which require a capacitor having a very short charging time (e.g. on the order of a nanosecond or less). It is also desirable that the capacitor have as high a value as possible under a bias voltage of either polarity. For this purpose, an MOS capacitor may be formed at a surface portion of a silicon-on-insulator (e.g. silicon-on-sapphire (SOS)) structure, in which a surface insulator (e.g. oxide layer) forms the capacitor dielectric between a topside plate (e.g. doped polysilicon or metal) layer and an underlying plate layer (e.g. a doped silicon region).
In many silicon-on-sapphire processes having a (epitaxial) silicon layer formed atop a sapphire support structure, it is possible to dope the epitaxial silicon layer at a sufficiently high impurity concentration, such that the depth of any depletion region formed in the silicon layer underlying the surface dielectric (oxide) is small relative to the thickness of the surface oxide. The capacitance of the resulting MOS capacitor structure is near its maximum attainable value under all bias conditions and the charging time is extremely small.
Some manufacturing processes, however, do not readily accommodate doping that portion of the semiconductor layer underlying the thin oxide at a high impurity concentration, so that the lower plate of an MOS capacitor must be formed by way of a lightly doped region. In such a capacitor structure, the lightly doped region will go into a deep depletion condition in response to the application of a high charge of a polarity corresponding to that of the doped material (high negative charge for a lightly doped N-semiconductor layer and high positive charge for a lightly doped P- semiconductor layer). For such a lightly doped structure, the depletion depth is typically an order of magnitude greater than the oxide thickness, which significantly reduces the transient capacitance.
One possible solution to such a deep depletion recovery problem would be to incorporate two such capacitors into the circuit and connect the capacitors in parallel, one capacitor having lightly doped N- material, contiguous with a more heavily doped N+ contact region, and another capacitor having lightly doped P- material, that is contiguous with a more heavily doped P+ contact region. Such a circuit configuration would ensure that the total capacitance of the capacitor pair is never below the dielectric (oxide) capacitance of either capacitor. Unfortunately, providing a pair of such capacitors means that the amount of semiconductor real estate used to form a single capacitor must be doubled for the two capacitor case.